Abstract: Although Network-on-Chip (NoC) [1] architectures present an interesting alternative to bus-based multiprocessor systems-on-chip (MPSoCs), they also need some effort to tackle communication contention problem. In this work the authors propose an efficient approach to application-specific irregular topology generation for contention-free NoC. There is taken advantage of a priori knowledge of the communication characteristic of the application (embedded system) to perform computation, communication scheduling and route generation with regard to performance constraints (Fig. 1). In the result there is obtained customized and minimal topology. The clear benefits of the authors' approach are: complete removal of network contention, simple router architecture without virtual channels, minimal network topology (in term of links necessary to guarantee contentionless communication), which meets system latency constraint, and input model of the system derived from co-synthesis of the embedded systems domain [6]. As demonstrated through experiments, this approach achieves far better performance than typical, random mesh networks and is comparable with well-known bandwidth-based solutions [3] (Tables 1, 3). In the resource-requirement field (interconnection fabric, Table 2) the authors' NoC is more saving than meshes (on average of 35%) and bandwidth-based custom topologies (on average of 25%).
B I B L I O G R A F I A[1] Bjerregaard T., Mahadevan S.: A survey of research and practices of network-on-chip, ACM Computing Surveys, 38 (1), 71-121, 2006.
[2] Lee H. G., Chang N., Ogras U. Y., Marculescu R.: On-Chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches, ACM Transactions on Design Automation of Electronic Systems, 12 (3), Article 23, 2007.
[3] Murali S., Meloni P., Angiolini F., Atienza D., Carta S., Benini L., De Micheli G., Raffo L.: Designing application-specific networks on chips with floorplan information, Int. Conf. on CAD, 355 - 362, 2006.
[4] Deniziak S., Tomaszewski R.: Adaptive routing protocols validation in NoC systems via rapid prototyping, Proceedings of the IEEE Human System Interaction, 115-120, 2008.
[5] Schelle G., Grunwald D.: Exploring FPGA Network on Chip implementations across various application and network loads, Intl Conference on Field Programmable Logic and Application, 41-46, 2008.
[6] Staunstrup J., Wolf W.: Hardware/software co-Design: Principles and practice, Kluwer Academic Publishers, Norwell, MA, USA, 1997.
[7] Deniziak S., Górski A.: Hardware/software co-synthesis of distributed embedded systems using genetic programming, Lecture Notes in Computer Science, Springer, 5216, 83-93, 2008.
[8] Dick R. P., Rhodes D. L., Wolf W.: TGFF: Task graphs for free, Int. Workshop on Hardware/Software Codesign, 97-101, 1997. 
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