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[22670] Artykuł: Application-oriented fast fault simulator for FPGAsCzasopismo: PROGRAMMABLE DEVICES AND SYSTEMS 2001 Strony: 241-246ISBN: 0-08-044081-9 Wydawca: PERGAMON-ELSEVIER SCIENCE LTD, THE BOULEVARD, LANGFORD LANE,, KIDLINGTON OX5 1GB, OXFORD, ENGLAND Opublikowano: 2001 Seria wydawnicza: IFAC WORKSHOP SERIES Autorzy / Redaktorzy / Twórcy
Grupa MNiSW: Materiały z konferencji międzynarodowej (zarejestrowane w Web of Science) Punkty MNiSW: 0 Klasyfikacja Web of Science: Proceedings Paper Web of Science Keywords: fault diagnosis  digital systems  simulators  testability  ternary logic  |
In this paper a new efficient approach to bit-parallel fault simulation for FPGA-based sequential systems is introduced and evaluated with the help of ISCAS89 benchmarks. Reduced Ordered Ternary Decision Diagrams (ROTDD) are used to describe functions of LUTs. This lead to substantial reduction of both, the number of simulated faults and calculations needed for simulation. Moreover, an approach presented in this paper is able to handle internal CLB faults in addition to interconnection faults. Copyright (C) 2001 IFAC.